1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display with a 2-port data polarity inverter and a method of driving the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a current consumption as well as improving an electromagnetic interference (EMI) characteristic.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmittance of each liquid crystal cell in accordance with a video signal, thereby displaying an image. An active matrix LCD including a switching device for each liquid crystal cell is suitable for displaying a dynamic image. The active matrix LCD uses a thin film transistor (TFT) as a switching device.
Since such an active matrix LCD is realized as a smaller device than a conventional cathode ray tube (CRT), it has been widely used for a monitor for a personal computer or a notebook computer as well as office automation equipment, such as a copy machine, and portable equipment, such as a cellular phone and a pager.
As shown in FIG. 1, a driving apparatus for the LCD includes a system driver 1 for converting an analog signal into digital video data, a data driver 3 for applying the video data to data lines DL of a liquid crystal panel 6, a gate driver 5 for sequentially driving gate lines GL of the liquid crystal panel 6, a timing controller 2 for controlling the data driver 3 and the gate driver 5, and a gamma voltage generator 4 for applying a gamma voltage to the data driver 3.
More specifically, the liquid crystal panel 6, a liquid crystal is injected between two glass substrates, and the gate lines GL and the data lines DL are formed on the lower glass substrate in such a manner to be perpendicular to each other. At each intersection between the gate lines GL and the data lines DL, a thin film transistor (TFT) for selectively applying an image inputted from the data lines DL to a liquid crystal cell Clc is provided. To this end, the TFT has a drain terminal connected to the gate line GL and a source terminal connected to the data line DL. The drain terminal of the TFT is connected to a pixel electrode of the liquid crystal cell Clc.
The system driver 1 converts an analog input image signal into a digital image signal suitable for the liquid crystal panel 6 and detects a synchronizing signal included in the image signal. A low voltage differential signal (LVDS) interface and a TTL interface are mainly used for data and control signal transmissions of the system driver 1. Alternatively, such interface functions, along with the timing controller 2, may be integrated into a single chip. In the LVDS interface, various data are compressed to a single line and inputted to the timing controller. An electric field induced in accordance with a current flow is formed at each line into which data are transmitted. An emission of this electric field causes an electromagnetic interference (EMI) phenomenon in which a signal transmitted to the adjacent lines is loaded with a noise, thereby interfering a normal operation. Due to this EMI phenomenon, a voltage of the data signal is lowered.
In order to overcome such an EMI phenomenon, a scheme of transmitting a differential signal has been suggested. Herein, the differential signal means a signal having a relationship as shown in FIG. 2 of the same amplitude and the inverse phase. When lines simultaneously transmitting positive and negative signals S+ and S− are adjacent to each other, electric fields generated from each of the adjacent lines are vanished due to their mutual action. More specifically, when the positive signal S+ is converted from a low level into a high level, the negative signal S− is converted from a high level into a low level. At this time, directions of the currents flowing in both lines become opposite to each other. Hence, electric fields generated in the opposite direction are cancelled by the Fleming's rule. This cancellation of the electric fields minimizes an emission of the electric field. Accordingly, a data signal having an original voltage can be applied to the timing controller.
The timing controller 2 applies red (R), green (G), and blue (B) data signals received from the system driver 1 to the data driver 3. Also, the timing controller 2 generates a dot clock Dclk and a gate start pulse GSP using horizontal/vertical synchronizing signals H and V and a data enable signal DE inputted from the system driver 1, thereby controlling a timing of the data driver 3 and the gate driver 5. The dot clock Dclk is applied to the data driver 3 while the gate start pulse GSP is applied to the gate driver 5.
The gate driver 5 includes a shift register for responding to the gate start pulse GSP inputted from the timing controller 2 to sequentially generate a scanning pulse, and a level shifter for shifting a voltage of the scanning pulse into a voltage level suitable for driving the liquid crystal cell. Video data at the data line DL are applied to a pixel electrode of the liquid crystal cell Clc by the TFT in response to the scanning pulse inputted from the gate driver 5.
The dot clock Dclk, along with the R, G, and B data signals from the controller 2, is inputted to the data driver 3. The data driver 3 latches the R, G, and B digital video data in synchronization with the dot clock Dclk and then corrects the latched data in accordance with a gamma voltage Vγ. Then, the data driver 3 converts data corrected by the gamma voltage Vγ into analog data and supplies it to the data line DL line by line.
The gamma voltage generator 4 generates a gamma voltage Vγ corresponding to data for a gray scale value based on an electro-optical characteristic of a liquid crystal display panel. The gamma voltage Vγ is a voltage divided in correspondence with a gray level by means of the gamma voltage generator 4. Thus, the gamma voltage Vγ generated from the gamma voltage generator 4 has a different voltage magnitude in correspondence with a gray scale value selected in an expressible range.
FIG. 3 is a detailed block diagram of the timing controller 2 shown in FIG. 1.
Referring to FIG. 3, the timing controller 2 generates desired signals for driving the LCD using the low voltage differential signal LVDS, the vertical and horizontal synchronizing signals H and V, and the data enable signal DE from the system driver 1.
The LVDS applies R, G, and B data signals through a data aligner 12 to the data driver 3. The vertical and horizontal synchronizing signals V and H apply timing control signals through a timing control signal generator to the data driver 3 and the gate driver 5.
Control signals required for the data driver 3 in these timing signals includes a source sampling clock SSC, a source output enable signal SOE, and a source start pulse SSP, etc. On the other hand, control signals required for the gate driver 5 include a gate shift clock GSC, a gate output enable signal GOE, and a gate start pulse GSP, etc.
The horizontal and vertical synchronizing signals H and V apply a polarity control signal through a polarity control signal generator 16 to the data driver 3 and the gate driver 5.
Such an LCD applies the data signals and the control signals from the system driver 1 through the timing controller 2 to the data driver 3 and the gate driver 5.
FIG. 4A is a detailed block diagram of a conventional REV transmitter within the timing controller 2.
Referring to FIG. 4A, the REV transmitter includes a data transition checker 30 for checking a transition of data, a REV signal summer 32 for detecting the number of signals in which a polarity of the data according to the data transition is changed to determine an output level, and a REV signal output 34 for receiving signals from the data transition checker 30 and the REV signal summer 32 to generate a signal for inverting output data.
More specifically, the data transition checker 30 consists of two flip-flops 36 and 38, and an exclusive logical sum gate XOR 40. The data transition checker 30 compares the current data flip-flop 36 with the previous data flip-flop 38 to check whether the data are changed into a high logic ‘1’ or a low logic ‘0’, and vice versa. If there is a transition of the data, the data transition part 30 outputs a high logic ‘1’. Conversely, if there is no transition of a data, the data transition part 30 outputs a low logic ‘0’. In this case, the data is sequentially compared regardless of the status of the data, i.e., even data EVEN or odd data ODD.
The REV signal summer 32 adds all the number of data having a data transition through the data transition part 30 by means of adders 42 and 44 with respect to each thirty-six R, G, and B even and odd data. At this time, a majority detector 46 determines whether the number of a high logic ‘1’ is more than eighteen, that is a half of the total number of the R, G, and B data. If the majority detector 46 determines that the number of a high logic ‘1’, which is an output with a data transition, is more than eighteen which is a half of thirty-six bits, the REV having a high logic ‘1’ is outputted. Conversely, if it determines that the number of a high logic ‘1’ is less than eighteen, the REV having a low logic ‘0’ is outputted.
The REV signal output 34 outputs a signal inverting output data when an output REV of the REV signal summer 32 is ‘1’ by using 2×1 multiplexors 48 and 50. In other words, in order to reduce a data transition amount when the number of the data transition is more than a half, the REV signal output 34 sends a data polarity-inverting signal for inverting an output signal to execute a transition of the output signal by {thirty-six -(data transition amount more than eighteen)} only. Accordingly, a REV signal for allowing unchanged input data to be recognized in a low logic while allowing inverted input data to be recognized in a high logic is inputted to the data driver 3.
FIG. 4B is a schematic block diagram of a REV receiver within the data driver 3.
Referring to FIG. 4B, the REV receiver 35 includes 2×1 multiplexors 48′ and 50′. Each of the input terminals of these multiplexors 48′ and 50′ is connected such that the signals outputted through the multiplexors 48 and 50 of the REV signal output 34 in FIG. 4A are inputted without a transition. Another input terminal thereof is connected such that the signals from the REV signal output 34 in FIG. 4A are inputted with an inverted state. The REV signals inputted to the multiplexors 48 and 50 are selected as the normal signals or the inverted signals by a high signal (‘1’) or a low signal (‘0’) from the majority detector 46 of the REV signal summer. The signals are then inputted to a latch circuit configuring the data driver 3, thereby inverting the polarities of the R, G and B data.
FIG. 5 schematically illustrates a conventional REV driving method.
Referring to FIG. 5, the current clock data are compared with the previous clock data with respect to thirty-six bits of the even and odd data EVEN and ODD, so that the number of data transition is reduced. In other words, 1st clock data CLK1 are compared with 2nd clock data CLK2 to determine whether there is a data transition.
Such a driving method is to compare transitions before and after 36-bit data inputted from the timing controller 2 to the liquid crystal module using a single port, and applying a signal for inverting the data if the data have more than eighteen bits. Conversely, an existing data is sent if the data have less than eighteen bits. However, the conventional driving method has a disadvantage in that, since the REV signal is selected in response to many data transitions, a current consumption is inevitably increased. As a result, a lot of electro-magnetic waves are generated.